The present invention relates to a block decoder and a semiconductor memory device including the same and, more particularly, to a block decoder which can prevent the malfunction of a semiconductor memory device due to a leakage current of the device.
Recently, there has been an increasing demand for semiconductor memory devices which can be electrically programmed and erased and do not need a refresh function of rewriting data at specific intervals. In order to develop large-capacity memory devices capable of storing a large amount of data, research has been conducted on the high integration of memory devices particularly flash memory.
Flash memory is generally classified into NAND flash memory and NOR flash memory. NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines and therefore exhibits an excellent random access time characteristic. NAND flash memory has a structure in which memory cells are connected in series, requiring only one contact per cell string, and therefore exhibits an excellent integration level characteristic. Accordingly, the NAND structure is generally used in high-integrated flash memory.
In general, a flash memory device requires a block decoder for selecting a memory cell array on a per block basis to perform program, read and erase operations of a memory cell.
FIG. 1 is a circuit diagram showing a block decoder of a conventional flash memory device.
Referring to FIG. 1, a NAND gate ND1 logically combines address signals XA, XB, XC and XD. A NAND gate ND2 logically combines an output signal of the NAND gate ND1 and a program precharge signal PGMPREb. When at least one of the address signals XA, XB, XC and XD is input at a low level, the NAND gate ND1 outputs a high-level signal. When at least one of the output signal of the NAND gate ND1 and the program precharge signal PGMPREb is input at a low level, the NAND gate ND2 outputs a high-level signal.
A NAND gate ND3 logically combines an output signal of the NAND gate ND2 and a block enable signal EN. When the block enable signal EN is applied at a low level, the NAND gate ND3 outputs a high-level signal to turn on a transistor N2. Thus, a node Q1 is reset.
A transistor N1 is turned in response to a precharge signal PRE, such that the output signal of the NAND gate ND2 is applied to the node Q1. The potential of the node Q1 functions as a block select signal BLKWL. Transistors N3 and N4 are turned on in response to first and second control signals GA and GB of a pumping voltage (Vpp) level, respectively, such that t he pumping voltage Vpp is applied to the node Q1. Thus, a block switch 20 operates in response to the potential of the node Q1, that is, the block select signal BLKWL. Accordingly, global word lines GWL<31;0> and word lines of a memory cell array 30 are connected.
A semiconductor memory device including the above block decoder selects only one memory cell block when operating and connects the selected memory cell block to the global word line. However, unselected memory cell blocks are disconnected from the global word line. A sensing margin of the selected memory cell block is decreased due to a bit line leakage current through a memory cell in the unselected memory cell blocks. That is, the leakage current is generated in which charges of a precharged bit line are discharged through the memory cell in the unselected memory blocks. Accordingly, an error may occur during a sensing operation of a selected memory cell.